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INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2456-4184 | Impact factor: 8.76 | ESTD Year: 2016 Scholarly open access journals, Peer-reviewed, and Refereed Journals, Impact factor 8.76 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool) , Multidisciplinary, Monthly, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI) |
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| Paper Title: | Design and Implementation of RISC-V Processor ALU using Multiplexers and LUT. |
| Authors Name: | Niranjana A , Nandhitha S T , Agnes Abina S , Srinivasan K |
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IJNRD_204786
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| Published Paper Id: | IJNRD2309039 |
| Published In: | Volume 8 Issue 9, September-2023 |
| DOI: | |
| Abstract: | RISC-V (Reduced Instruction Set Computing) is a high-performance Instruction Set Architecture (ISA) capable of performing CISC level functions. ALUs form the fundamental execution unit of any processor. The conventional ALU’s are designed using the combinational circuits like the adders, subtractors, multipliers, decoders etc.... Also, they are designed in such a way that it calculates the result each time for the selected operation and then assigns it to the output signal. This leads to more delay (because the operands are calculated only at that instant) and the increased computational complexity. The proposed multiplexer based ALU focuses on power optimization and reduces the delay in the execution of the processor which results in improved performance of the processor. Multiplexers are used instead of other combinational circuits where it uses the registers to store the intermediate results and for selecting the corresponding output signal based on the selected operation on the same data. Hence the ALU designed using these multiplexers will have less delay when compared to the conventional ALU’s. |
| Keywords: | RISC (Reduced Instruction Set Computing) V, ALU, Multiplexer, LUT, Xilinx Vivado, Verilog. |
| Cite Article: | "Design and Implementation of RISC-V Processor ALU using Multiplexers and LUT.", International Journal of Novel Research and Development (www.ijnrd.org), ISSN:2456-4184, Vol.8, Issue 9, page no.a341-a344, September-2023, Available :http://www.ijnrd.org/papers/IJNRD2309039.pdf |
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2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.76 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
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Published Paper ID:IJNRD2309039 Registration ID: 204786 Published In: Volume 8 Issue 9, September-2023 DOI (Digital Object Identifier): Page No: a341-a344 Country: Chennai, Tamil Nadu, India Research Area: Electronics & Communication Engg. Publisher : IJ Publication Published Paper URL : https://www.ijnrd.org/viewpaperforall?paper=IJNRD2309039 Published Paper PDF: https://www.ijnrd.org/papers/IJNRD2309039 |
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