Paper Title
IP Level Verification of Ethernet Protocol using Wishbone Interface
Article Identifiers
Authors
Peddisetty Rupavathi , Dr. Gannera Mamatha
Keywords
WISHBONE bus, Media Access Control, Verification Methodology Manual, System Verilog, Assertions, UVM, Verilog.
Abstract
SOC (System- on-a-Chip) is the international VLSI evolution paradigm that's nowadays conquering IC evolution. This document describes the verification of Ethernet MAC (Media Access Control) applying UVM (Universal Verification Approach), the most widely used verification methodology. Ethernet frames are furthered to PHY over MII (Media Independent Interface) by MAC, while frames from PHY are admitted by MAC through the identical interface. An elegant system of validating MAC characteristics, similar as frame transmission and reception, is through IP verification achieves coverage driven verification at its best by exercising factory and configuration mechanisms, coverage measures, and self- checking, which shortens the time needed for design verification.
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How To Cite (APA)
Peddisetty Rupavathi & Dr. Gannera Mamatha (December-2022). IP Level Verification of Ethernet Protocol using Wishbone Interface. INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 7(12), b250-b255. https://ijnrd.org/papers/IJNRD2212125.pdf
Issue
Volume 7 Issue 12, December-2022
Pages : b250-b255
Other Publication Details
Paper Reg. ID: IJNRD_184860
Published Paper Id: IJNRD2212125
Downloads: 000121989
Research Area: Engineering
Country: Kurnool, Andhra Pradesh, India
Published Paper PDF: https://ijnrd.org/papers/IJNRD2212125.pdf
Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2212125
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Journal Name: INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT(IJNRD)
ISSN: 2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar | ESTD YEAR: 2016
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This work is licensed under a Creative Commons Attribution 4.0 International License and The Open Definition
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