A Secure FPGA Implementation of AES-CTR Encryption with AXI Interface and Statistical Image Analysis

Registration ID: IJNRD_328142

Published ID: IJNRD2608353

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T L SPANDANA, Prasanth Kumar Akkireddi, Mani Endigabilli, Emaja Asi, Kiran Kumar Bonu

Advanced Encryption Standard (AES), Counter Mode (CTR), FPGA Hardware Acceleration, Image Encryption, PYNQ-Z2 Platform, Cryptographic Security Analysis.

— Data transmission or storage typically requires a means encrypting data. Encryption is a process whereby data is encoded so that it cannot be read or understood without a key. While current implementations of data encryption use the Advanced Encryption Standard (AES), most implementations rely heavily on software-based solutions that often introduce significant (i.e., increased) latency, low (i.e., reduced) throughput, and have no support for hardware acceleration for real-time applications. Furthermore, beyond the fact that very few studies provide statistical validation of the strength of encryption, most studies do not provide statistical evaluation (i.e., using statistical analysis tools) of the strength of the encryption. In this paper, we present a Counter (CTR) mode FPGA implementation of an AES encryption engine. The proposed implementation is based upon the PYNQ-Z2 FPGA development platform, which is built upon the Xilinx Zynq-7000 (FPGA)—using Verilog HDL for the design. The AES-CTR encryption engine includes an AXI-compliant interface between the processing system (PS) and programmable logic (PL) to provide efficient intercommunication between the two subsystems. Using the Xilinx Vivado Design Suite (hardware synthesis, timing analysis, power analysis), we determine and report on the performance of the new implementation. The results were validated for the new socket implementation using statistical analyses such as entropy, correlation coefficient, NPCR, UACI, PSNR and SSIM within the MATLAB environment. Based on the findings, our proposed FPGA-based and software-based encryption implementations offer improved data encryption performance and increase the degree of statistical randomness.

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T L SPANDANA, Prasanth Kumar Akkireddi, Mani Endigabilli, Emaja Asi, & Kiran Kumar Bonu (August-2026). A Secure FPGA Implementation of AES-CTR Encryption with AXI Interface and Statistical Image Analysis . INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 11(8), d519-d525. https://ijnrd.org/papers/IJNRD2608353.pdf

Volume 11 Issue 8, August-2026

Pages : d519-d525

Paper Reg. ID: IJNRD_328142

Published Paper Id: IJNRD2608353

Research Area: Other area not in list

Author Type: Indian Author

Country: VISAKHAPATNAM, Andhra Pradesh, India

Published Paper PDF: https://ijnrd.org/papers/IJNRD2608353.pdf

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