An Area-Efficient Universal Cryptography Processor for Smart Cards

Registration ID: IJNRD_222582

Published ID: IJNRD2405729

DOI: Click Here to Get

Priyansh Rai , Lagan Sharma , Divyanshu Gupta

Cryptography, Computer Security, Microprocessors, Smart Cards

Cryptography circuits in smart cards and portable electronic devices are crucial for user authentication and secure data communication. These circuits need to be compact, energy-efficient, capable of handling multiple cryptographic algorithms, and deliver good performance. This paper introduces, for the first time, a hardware implementation of three standard cryptography algorithms on a universal architecture. The micro coded cryptography processor is designed for smart card applications, supporting both private key and public key algorithms while meeting the required power and performance standards. Impressively, it is as small as 2.25 mm² using 0.18-µm 6LM CMOS technology. A new algorithm can be implemented simply by updating the contents of the memory blocks, which are made with ferroelectric RAM (FeRAM). FeRAM allows for nonvolatile storage of configuration bits, which only need to be changed when a new algorithm is introduced.

Published Paper   E-Certificate

Priyansh Rai, Lagan Sharma, & Divyanshu Gupta (May-2024). An Area-Efficient Universal Cryptography Processor for Smart Cards. INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 9(5), h90-h96. https://ijnrd.org/papers/IJNRD2405729.pdf

Volume 9 Issue 5, May-2024

Pages : h90-h96

Paper Reg. ID: IJNRD_222582

Published Paper Id: IJNRD2405729

Downloads: 000122002

Research Area: Electronics & Communication Engg. 

Country: Ghaziabad, Uttar Pradesh, India

Published Paper PDF: https://ijnrd.org/papers/IJNRD2405729.pdf

Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2405729

Journal Name: INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT(IJNRD)

ISSN: 2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar | ESTD YEAR: 2016

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