Design Of Low Power Synchronous Counter Using Adiabatic Techniques

Design Of Low Power Synchronous Counter Using Adiabatic Techniques

Registration ID: IJNRD_219357

Published ID: IJNRD2404745

DOI: Click Here to Get

V. Hari Krishna , V. Bindu Priya , G.Raghu Ram , Ch.Dhanush , I.Sesha Talpa Sai

Complementary Metal Oxide Semiconductor(CMOS), N-channel metal-oxide semiconductor (NMOS), P-channel metal-oxide semiconductor (PMOS),Efficient Charge Recovery Logic(ECRL),Direct Current Diode Based Positive Feed Back Logic(DC DB PFAL)

In the designing of VLSI circuit’s power dissipation has become a major concern. So, by reducing power dissipation we can attain our low power circuit. Excessive power consumption can negatively impact circuit reliability, resulting in higher maintenance costs, which elevates the cost of cooling system and packaging. As, with the advancement of electronic circuits which are dealing with the digital circuitry are implemented with the use of CMOS technology. The simultaneous pursuit of high performance and low power consumption remains a paramount concern in contemporary integrated circuit design. Various adiabatic techniques can be used for minimizing the power Consumption. In the quest for ever-more efficient digital integrated circuits (ICs), adiabatic logic techniques have emerged as a promising alternative to traditional CMOS logic design. Adiabatic techniques aim to reduce power dissipation during signal transitions, potentially leading to significant improvements in circuit performance and energy efficiency. To evaluate their effectiveness, these techniques have been compared against established CMOS logic design principles in the context of specific circuit implementations, such as synchronous counters. The sequential circuit (Synchronous counter) is implemented with the use of adiabatic techniques like ecrl, 2n-2n2p etc

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"Design Of Low Power Synchronous Counter Using Adiabatic Techniques", IJNRD - INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT (www.IJNRD.org), ISSN:2456-4184, Vol.9, Issue 4, page no.h379-h388, April-2024, Available :https://ijnrd.org/papers/IJNRD2404745.pdf

Volume 9 Issue 4, April-2024

Pages : h379-h388

Paper Reg. ID: IJNRD_219357

Published Paper Id: IJNRD2404745

Downloads: 000121162

Research Area: Engineering

Country: Palnadu , District, Andhra Pradesh, India

Published Paper PDF: https://ijnrd.org/papers/IJNRD2404745.pdf

Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2404745

Journal Name: INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT(IJNRD)

ISSN: 2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar | ESTD YEAR: 2016

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This work is licensed under a Creative Commons Attribution 4.0 International License and The Open Definition

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