Paper Title
A Review On Design and Analysis of Sequential Circuits Using Low Power Adiabatic Techniques
Article Identifiers
Authors
A. Gangadhar , O. Yashwanth Roshan , J. Reena Christiana
Keywords
Very large-scale integration (VLSI), complementary metal-oxide semi- conductor (CMOS), p-channel metal-oxide semiconductor (PMOS), n-channel metal-oxide semiconductor (NMOS), positive feedback adiabatic logic (PFAL), efficient charge recovery logic (ECRL), simulation program with integrated circuit emphasis (SPICE)
Abstract
Power consumption in a circuit has been a major problem in the usage of devices and leads to serious issues of over battery or supply drain. Reducing power consumption in real-world applications is crucial for battery life and thermal management in electronic devices. This paper proposes a logic-independent approach to achieve power reduction in sequential circuits, a fundamental building block in digital systems. We look forward to use the power reduction techniques. we use the adiabatic logic principle so as to reduce the power consumption across a circuit so as to reduce the power dissipation in a device. The energy recovery reduces the power consumption and reuses the energy through reversible logic. The aim of study is to design and implement sequential circuits using such adiabatic techniques using TANNER TOOLS software.
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How To Cite (APA)
A. Gangadhar , O. Yashwanth Roshan, & J. Reena Christiana (April-2024). A Review On Design and Analysis of Sequential Circuits Using Low Power Adiabatic Techniques . INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 9(4), f837-f846. https://ijnrd.org/papers/IJNRD2404600.pdf
Issue
Volume 9 Issue 4, April-2024
Pages : f837-f846
Other Publication Details
Paper Reg. ID: IJNRD_219220
Published Paper Id: IJNRD2404600
Downloads: 000121978
Research Area: Engineering
Country: NARASARAOPET, Andhra Pradesh, India
Published Paper PDF: https://ijnrd.org/papers/IJNRD2404600.pdf
Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2404600
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