DESIGN OF LOW-POWER SHIFT REGISTER USING GDI TECHNIQUE

Registration ID: IJNRD_216446

Published ID: IJNRD2403482

DOI: Click Here to Get

K.Kalaichelvi , C.Nivashini

Large-scale GDI circuits, Cryogenic, RSFQ logic, GDI buffer chain.

For the purpose of testing large-scale GDI circuits with delay-line clocking, propose and demonstrate a shift register. An essential circuit block in cryogenic studies is a pair of serializes, or parallel-to-serial converters, and deserializers, or serial-to-parallel converters. For example, apparatus like a cryostat and cry probe restrict the amount of available input/output (I/O) cables. Therefore, it is essential to minimize the number of I/O cables using a Sir/Des, particularly when testing a large-scale superconductor circuit. Shift registers, which hold data during serial-to-parallel (S2P) and parallel-to-serial (P2S) conversion, are used in RSFQ logic as serializes and deserializers. Regarding GDI logic, we have already suggested and illustrated the feedback-type SR, in which a shift register-like GDI buffer chain with feedback paths functions. However, because feedback routes in delay-line clocking are challenging to create due to the low latency, this Ser/Des was designed for four-phase clocking and does not function in that mode. As a result, we create the GDI hybrid SR, a unique SR for testing delay-line-clocked GDI circuits that combines GDI and RSFQ technology.

Published Paper   E-Certificate

K.Kalaichelvi & C.Nivashini (March-2024). DESIGN OF LOW-POWER SHIFT REGISTER USING GDI TECHNIQUE . INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 9(3), e657-e669. https://ijnrd.org/papers/IJNRD2403482.pdf

Volume 9 Issue 3, March-2024

Pages : e657-e669

Paper Reg. ID: IJNRD_216446

Published Paper Id: IJNRD2403482

Downloads: 000121982

Research Area: Electronics & Communication Engg. 

Country: Karur, Tamilnadu, India

Published Paper PDF: https://ijnrd.org/papers/IJNRD2403482.pdf

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