Paper Title
Design and analysis of two stage operational amplifier
Article Identifiers
Authors
NEHA
Keywords
CMOS , NEGATIVE CAPACITANCE GENERATION, FLIPPED VOLTAGE FOLLOWER
Abstract
This research paper presents the design and analysis of two stage CMOS structure with enhanced gain-bandwidth product (GBW) , high slew rate and good phase margin. In this paper, the combined use of negative capacitance and Flipped voltage buffer (FVF) proves quite useful for frequency compensation of MOS amplifiers. This method ensures stability without degrading circuit performance at higher frequencies and is well suited for low power and low voltage analog designs . The use of Negative capacitance lowers the parasitic capacitances of the preceding stage and thereby achieves significant improvement in Gain bandwidth product. The flipped voltage follower acts a voltage buffer and exploits pole –zero cancellation technique. The required compensation capacitor is very small so it can save chip area. The workability of the proposed circuit will be verified by using LT SPICE simulation tool with CMOS 0.18µm process parameters.
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How To Cite (APA)
NEHA (December-2023). Design and analysis of two stage operational amplifier. INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 8(12), b685-b692. https://ijnrd.org/papers/IJNRD2312186.pdf
Issue
Volume 8 Issue 12, December-2023
Pages : b685-b692
Other Publication Details
Paper Reg. ID: IJNRD_211036
Published Paper Id: IJNRD2312186
Downloads: 000121980
Research Area: Engineering
Country: Aurangabad, Bihar, India
Published Paper PDF: https://ijnrd.org/papers/IJNRD2312186.pdf
Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2312186
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This work is licensed under a Creative Commons Attribution 4.0 International License and The Open Definition


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