FPGA Design of Effective Detection Low Power Architecture for Recycled ICs

Registration ID: IJNRD_202454

Published ID: IJNRD2307451

DOI: Click Here to Get

Varsha J , Bakialakshmi D

RO-Based Sensor, CAF-Based Sensor, SAF-Based Sensor.

The counterfeiting and exercise of integrated circuits (ICs) became major problems in recent years, doubtless impacting the safety and dependableness of electronic systems sure for military, financial, or alternative crucial applications. With identical practicality and packaging, it'd be very troublesome to differentiate recycled ICs from unused ICs. In this paper, two varieties of on-chip light-weight sensors area unit planned to identify recycled ICs by measurement circuit usage time once utilized in the sector. Recycled ICs detection supported aging in Ring Oscillators (ROs-based) and Anti-Fuse (AF-based) square measure the two techniques given during this paper. The planned methodology is meant mistreatment Verilog compound, simulated mistreatment Modalism and synthesized pattern Xilinx code.

Published Paper   E-Certificate

Varsha J & Bakialakshmi D (July-2023). FPGA Design of Effective Detection Low Power Architecture for Recycled ICs. INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 8(7), e442-e446. https://ijnrd.org/papers/IJNRD2307451.pdf

Volume 8 Issue 7, July-2023

Pages : e442-e446

Paper Reg. ID: IJNRD_202454

Published Paper Id: IJNRD2307451

Downloads: 000121991

Research Area: Electronics & Communication Engg. 

Country: Kovilpatti, Tamilnadu, India

Published Paper PDF: https://ijnrd.org/papers/IJNRD2307451.pdf

Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2307451

Journal Name: INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT(IJNRD)

ISSN: 2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar | ESTD YEAR: 2016

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