DESIGN OF PLL USING LOW POWER APPLICATION

Registration ID: IJNRD_199094

Published ID: IJNRD2306328

DOI: http://doi.one/10.1729/Journal.36335

Nagaveni.G , Dr Kiran Gupta

VCO, Phase Locked Loop,Tanner EDA,Phase Noise

The project proposes the design of phase locked loop (PLL) using an improved performance ring voltage-controlled oscillator (VCO). The modified ring VCO topology incorporates a tail current source and cross-coupled transistors to enhance linearity and reduce phase compared to conventional PLLs, making it well-suited for high-performance communication systems. The results validate the effectiveness of the modified ring VCO topology in enhancing the performance of PLL-based applications.

Published Paper   E-Certificate

Nagaveni.G & Dr Kiran Gupta (June-2023). DESIGN OF PLL USING LOW POWER APPLICATION. INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 8(6), d283-d289. http://doi.one/10.1729/Journal.36335

Volume 8 Issue 6, June-2023

Pages : d283-d289

Paper Reg. ID: IJNRD_199094

Published Paper Id: IJNRD2306328

Downloads: 000121986

Research Area: Electronics & Communication Engg. 

Country: KANAKA NAGAR RT NAGAGR, BANGALORE KARNATAKA, India

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Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2306328

Crossref DOI: http://doi.one/10.1729/Journal.36335

Journal Name: INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT(IJNRD)

ISSN: 2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar | ESTD YEAR: 2016

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