Design of 16-bit Adder, Multiplier and ALU using Reversible Logic Gates

Registration ID: IJNRD_198667

Published ID: IJNRD2306167

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Padala Jayakrishna Chary , A. Lahari , A. Mahesh , G. Nagireddy

Adder, Multiplier, Arithmetic and Logic unit (ALU), power dissipation, application specific reversibility

Increasing demand for reduction in power dissipation in digital computer system has led to new mode of computation for digital design giving birth to reversible computing. Its main objective is low power dissipation in logical elements but can have some other advantages like error prevention and data security. In present-day, reversible logic has bring out to be an optimistic computing model having applications in low power CMOS, nanotechnology, quantum computing and DNA computing. This paper presents about various purposed schemes used to design a 16-bit Adder, 16×16 Multiplier and Arithmetic & Logical Unit using Reversible Logic Gates. The reversible Adders, Multipliers and ALUs are optimized in terms of total quantum cost, number of ancillary inputs, number of garbage outputs and hardware complexity.

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Padala Jayakrishna Chary, A. Lahari, A. Mahesh, & G. Nagireddy (June-2023). Design of 16-bit Adder, Multiplier and ALU using Reversible Logic Gates. INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 8(6), b590-b595. https://ijnrd.org/papers/IJNRD2306167.pdf

Volume 8 Issue 6, June-2023

Pages : b590-b595

Paper Reg. ID: IJNRD_198667

Published Paper Id: IJNRD2306167

Downloads: 000121978

Research Area: Electronics & Communication Engg. 

Country: Hyderabad, Telangana, India

Published Paper PDF: https://ijnrd.org/papers/IJNRD2306167.pdf

Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2306167

Journal Name: INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT(IJNRD)

ISSN: 2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar | ESTD YEAR: 2016

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