Ultra-Low Power Approximate Multipliers Using Energy Recovery Logic

Registration ID: IJNRD_191219

Published ID: IJNRD2304284

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Galla Naga manikanta , Bathina Pavani , Durbesula Meeravali , Chalasani Devesh chowdary , K.Srilakshmi

Approximate computing, adiabatic logic, CMOS, Positive feedback adiabatic logic, power dissipation.

Multipliers are crucial components in digital signal processors, especially in applications like multimedia, machine learning, and data mining. In such applications, approximate circuits can be used to reduce area, power, and delay while still maintaining acceptable levels of accuracy. Adiabatic logic is a low-power technique that can be employed to further reduce power consumption. In this study, approximate 4-bit array multipliers were designed using both traditional CMOS and PFAL adiabatic logic, and then implemented in Cadence virtuoso. The results showed that the PFAL circuits achieved power savings of approximately 59% compared to CMOS logic. This highlights the potential of PFAL circuits for battery-operated portable systems where power consumption is a critical concern.

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Galla Naga manikanta, Bathina Pavani, Durbesula Meeravali, Chalasani Devesh chowdary, & K.Srilakshmi (April-2023). Ultra-Low Power Approximate Multipliers Using Energy Recovery Logic. INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 8(4), c641-c645. https://ijnrd.org/papers/IJNRD2304284.pdf

Volume 8 Issue 4, April-2023

Pages : c641-c645

Paper Reg. ID: IJNRD_191219

Published Paper Id: IJNRD2304284

Downloads: 000121980

Research Area: Electronics & Communication Engg. 

Country: Krishna District, Andhra Pradesh, India

Published Paper PDF: https://ijnrd.org/papers/IJNRD2304284.pdf

Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2304284

Journal Name: INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT(IJNRD)

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