INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2456-4184 | Impact factor: 8.76 | ESTD Year: 2016
Scholarly open access journals, Peer-reviewed, and Refereed Journals, Impact factor 8.76 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool) , Multidisciplinary, Monthly, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI)
Multipliers are crucial components in digital signal processors, especially in applications like multimedia, machine learning, and data mining. In such applications, approximate circuits can be used to reduce area, power, and delay while still maintaining acceptable levels of accuracy. Adiabatic logic is a low-power technique that can be employed to further reduce power consumption. In this study, approximate 4-bit array multipliers were designed using both traditional CMOS and PFAL adiabatic logic, and then implemented in Cadence virtuoso. The results showed that the PFAL circuits achieved power savings of approximately 59% compared to CMOS logic. This highlights the potential of PFAL circuits for battery-operated portable systems where power consumption is a critical concern.
"Ultra-Low Power Approximate Multipliers Using Energy Recovery Logic", International Journal of Novel Research and Development (www.ijnrd.org), ISSN:2456-4184, Vol.8, Issue 4, page no.c641-c645, April-2023, Available :http://www.ijnrd.org/papers/IJNRD2304284.pdf
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2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.76 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
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