DESIGN AND COMPARITIVE ANALYSIS OF BINARY AND TERNARY SRAM CELL

Registration ID: IJNRD_191104

Published ID: IJNRD2304264

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S. Vardhan Kumar , A. Nandini , A. Dhakshayini , Ch. Kavya , T. Venkata Lakshmi

Binary SRAMs, Ternary SRAMs, Power dissipation, Delay, Area, Average Power,

One of the biggest problems in portable applications, which are always in demand and include laptops, mobile phones, etc., is a low power circuit. Static Random Memory (SRAM) consumes a sizable portion of a system-on-a-chip (Soc) and considerably adds to the chip's overall power consumption, which is why efforts are made to develop low power Recurrently, there is a demand for the design of high performance and low-power memory circuits. Both high-performance processors and portable handheld devices require. SRAM as a key component. With ternary inverters and inverters, we are creating SRAM. cells. The binary number system's fundamental unit is 2. (0,1). The base number for the ternary numeral system is 3. (0,1 and 2). In the proposed project, binary and ternary SRAMs both from different cells will be compared, and performance traits such. propagation delay, power dissipation, as well as energy delay product will be monitored and determined.

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S. Vardhan Kumar, A. Nandini, A. Dhakshayini, Ch. Kavya, & T. Venkata Lakshmi (April-2023). DESIGN AND COMPARITIVE ANALYSIS OF BINARY AND TERNARY SRAM CELL. INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 8(4), c502-c505. https://ijnrd.org/papers/IJNRD2304264.pdf

Volume 8 Issue 4, April-2023

Pages : c502-c505

Paper Reg. ID: IJNRD_191104

Published Paper Id: IJNRD2304264

Downloads: 000121980

Research Area: Engineering

Country: Krishna District, Andhra Pradesh, India

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