Paper Title
Design And Analysis Of Approximate Multiplier With Reconfigurable Reduction
Article Identifiers
Registration ID: IJNRD_188928
Published ID: IJNRD2303212
DOI: http://doi.one/10.1729/Journal.33774
Authors
G.Siva Prasad , Mrs.V.Sreelakshmi , B.Divya , Ch.N.B.Bhavani , B.Pratap Reddy
Keywords
Approximate Multiplier, Low Power, Image processing, Neural Networks, Internet of things.
Abstract
For a variety of different applications, including processing of image, expert systems, the smart things, and processing of digital systems, low-power and high-speed electronic system are now required. In a general multiplying operation account for most of the data processing time. The potential solution for hardware that operates quickly and efficiently is approximate multiplier. The approximate multiplier has developed into a key arithmetic element for many applications over the past ten years. So, Identifying a suitable multiplier which makes the trade-off between power and efficiency is important. In this Paper, We compared different Approximate Multipliers and find the suitable one.
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How To Cite
"Design And Analysis Of Approximate Multiplier With Reconfigurable Reduction", IJNRD - INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT (www.IJNRD.org), ISSN:2456-4184, Vol.8, Issue 3, page no.c72-c78, March-2023, Available :https://ijnrd.org/papers/IJNRD2303212.pdf
Issue
Volume 8 Issue 3, March-2023
Pages : c72-c78
Other Publication Details
Paper Reg. ID: IJNRD_188928
Published Paper Id: IJNRD2303212
Downloads: 000121160
Research Area: Electronics & Communication Engg.Â
Country: Bapatla, Andhra Pradesh, India
Published Paper PDF: https://ijnrd.org/papers/IJNRD2303212.pdf
Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2303212
DOI: http://doi.one/10.1729/Journal.33774
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Journal Name: INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT(IJNRD)
ISSN: 2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar | ESTD YEAR: 2016
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