Paper Title
Multi Threshold CMOS Technique for designing of Low Power 4 Bit ALU and Combinational Circuits
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Registration ID: IJNRD_182953
Published ID: IJNRD2209092
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Keywords
CMOS, Delay, leakage, MTCMOS, Power Dissipation
Abstract
Exponential increase in the transistor density on a single substrate in an integrated circuit has paved the way for tremendous growth in the semiconductor industry. Very Large Scale Integration (VLSI) of these transistors on a single substrate boosts performance but also causes multiple issues related to delay and power consumption. It is important to boost performance but keep the trade-offs related to delay and power to a minimum. This has resulted in researchers moving towards low-power design techniques. Such techniques are different from conventional design techniques in such a way that power is consumed as and when needed. This helps in minimizing the total power consumed by any circuit. The work presented in this paper aims to present the capability of the multiple threshold complementary metal oxide semiconductor (MTCMOS) technique to achieve low power consumption with approximately the same delay time in a single circuit. Standard arithmetic and logic circuits have been simulated at the 180 nm technology node and critical parameters, namely power, and delay, have been calculated using the MTCMOS technique and compared with conventional CMOS design. It is shown that by using transistors of different thresholds (as in the MTCMOS technique) power consumption is significantly reduced.
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How To Cite (APA)
Prachi & Professor KL Purshnani (September-2022). Multi Threshold CMOS Technique for designing of Low Power 4 Bit ALU and Combinational Circuits. INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 7(9), 789-795. https://ijnrd.org/papers/IJNRD2209092.pdf
Issue
Volume 7 Issue 9, September-2022
Pages : 789-795
Other Publication Details
Paper Reg. ID: IJNRD_182953
Published Paper Id: IJNRD2209092
Research Area: Electronics & Communication Engg.รย
Author Type: Indian Author
Country: GHAZIABAD, Uttar Pradesh, India
Published Paper PDF: https://ijnrd.org/papers/IJNRD2209092.pdf
Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2209092
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