Multi Threshold CMOS Technique for designing of Low Power 4 Bit ALU and Combinational Circuits

Multi Threshold CMOS Technique for designing of Low Power 4 Bit ALU and Combinational Circuits

Registration ID: IJNRD_182953

Published ID: IJNRD2209092

DOI: Click Here to Get

Prachi , Professor KL Purshnani

CMOS, Delay, leakage, MTCMOS, Power Dissipation

Exponential increase in the transistor density on a single substrate in an integrated circuit has paved the way for tremendous growth in the semiconductor industry. Very Large Scale Integration (VLSI) of these transistors on a single substrate boosts performance but also causes multiple issues related to delay and power consumption. It is important to boost performance but keep the trade-offs related to delay and power to a minimum. This has resulted in researchers moving towards low-power design techniques. Such techniques are different from conventional design techniques in such a way that power is consumed as and when needed. This helps in minimizing the total power consumed by any circuit. The work presented in this paper aims to present the capability of the multiple threshold complementary metal oxide semiconductor (MTCMOS) technique to achieve low power consumption with approximately the same delay time in a single circuit. Standard arithmetic and logic circuits have been simulated at the 180 nm technology node and critical parameters, namely power, and delay, have been calculated using the MTCMOS technique and compared with conventional CMOS design. It is shown that by using transistors of different thresholds (as in the MTCMOS technique) power consumption is significantly reduced.

Published Paper   E-Certificate

"Multi Threshold CMOS Technique for designing of Low Power 4 Bit ALU and Combinational Circuits", IJNRD - INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT (www.IJNRD.org), ISSN:2456-4184, Vol.7, Issue 9, page no.789-795, September-2022, Available :https://ijnrd.org/papers/IJNRD2209092.pdf

Volume 7 Issue 9, September-2022

Pages : 789-795

Paper Reg. ID: IJNRD_182953

Published Paper Id: IJNRD2209092

Downloads: 000121159

Research Area: Electronics & Communication Engg. 

Country: GHAZIABAD, Uttar Pradesh, India

Published Paper PDF: https://ijnrd.org/papers/IJNRD2209092.pdf

Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD2209092

Journal Name: INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT(IJNRD)

ISSN: 2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar | ESTD YEAR: 2016

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