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ISSN Approved Journal No: 2456-4184 | Impact factor: 8.76 | ESTD Year: 2016
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Impact Factor : 8.76

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Paper Title: Multi Threshold CMOS Technique for designing of Low Power 4 Bit ALU and Combinational Circuits
Authors Name: Prachi , Professor KL Purshnani
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Published Paper Id: IJNRD2209092
Published In: Volume 7 Issue 9, September-2022
Abstract: Exponential increase in the transistor density on a single substrate in an integrated circuit has paved the way for tremendous growth in the semiconductor industry. Very Large Scale Integration (VLSI) of these transistors on a single substrate boosts performance but also causes multiple issues related to delay and power consumption. It is important to boost performance but keep the trade-offs related to delay and power to a minimum. This has resulted in researchers moving towards low-power design techniques. Such techniques are different from conventional design techniques in such a way that power is consumed as and when needed. This helps in minimizing the total power consumed by any circuit. The work presented in this paper aims to present the capability of the multiple threshold complementary metal oxide semiconductor (MTCMOS) technique to achieve low power consumption with approximately the same delay time in a single circuit. Standard arithmetic and logic circuits have been simulated at the 180 nm technology node and critical parameters, namely power, and delay, have been calculated using the MTCMOS technique and compared with conventional CMOS design. It is shown that by using transistors of different thresholds (as in the MTCMOS technique) power consumption is significantly reduced.
Keywords: CMOS, Delay, leakage, MTCMOS, Power Dissipation
Cite Article: "Multi Threshold CMOS Technique for designing of Low Power 4 Bit ALU and Combinational Circuits", International Journal of Novel Research and Development (www.ijnrd.org), ISSN:2456-4184, Vol.7, Issue 9, page no.789-795, September-2022, Available :http://www.ijnrd.org/papers/IJNRD2209092.pdf
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ISSN: 2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.76 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publication Details: Published Paper ID:IJNRD2209092
Registration ID: 182953
Published In: Volume 7 Issue 9, September-2022
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Page No: 789-795
Country: GHAZIABAD, Uttar Pradesh, India
Research Area: Electronics & Communication Engg. 
Publisher : IJ Publication
Published Paper URL : https://www.ijnrd.org/viewpaperforall?paper=IJNRD2209092
Published Paper PDF: https://www.ijnrd.org/papers/IJNRD2209092
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ISSN: 2456-4184
Impact Factor: 8.76 and ISSN APPROVED
Journal Starting Year (ESTD) : 2016

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