COMPARATIVE ANALYSIS OF CMOS AND ADIABATIC ECRL CIRCUITS

Registration ID: IJNRD_170144

Published ID: IJNRD1711007

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Varsha R D , Dr. Rajashri Khanai

logic, Partially adiabatic, Fully adiabatic, PFAL, ECRL

Power consumption is of utmost importance in the field of semiconductor industry. Several techniques have been employed to reduce the power consumption in the electronic devices one of which is the adiabatic logic. There are two types of adiabatic circuits, partially adiabatic and fully adiabatic circuits. In this thesis work we have used partially adiabatic circuits. Positive Feedback Adiabatic Logic and Efficient Charge Recovery logic (ECRL) are the two prominent partially adiabatic logic styles. Several circuits were implemented using conventional CMOS and adiabatic ECRL logic and the performance of the circuits is compared in terms of power consumption, delay and transistor count. It is found that there is a significant difference in the parameters compared. The circuits are implemented in cadence virtuoso 6.1.5 and simulation is carried out in spectre MMSIM131.

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Varsha R D & Dr. Rajashri Khanai (November-2017). COMPARATIVE ANALYSIS OF CMOS AND ADIABATIC ECRL CIRCUITS. INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 2(11), 37-42. https://ijnrd.org/papers/IJNRD1711007.pdf

Volume 2 Issue 11, November-2017

Pages : 37-42

Paper Reg. ID: IJNRD_170144

Published Paper Id: IJNRD1711007

Downloads: 000121988

Research Area: Engineering

Country: Belagavi, karnataka, India

Published Paper PDF: https://ijnrd.org/papers/IJNRD1711007.pdf

Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD1711007

Journal Name: INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT(IJNRD)

ISSN: 2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar | ESTD YEAR: 2016

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