Paper Title
Design & Implementation of Self Time Dummy Replica Technique in 128x128 Low Voltage SRAM
Article Identifiers
: Authors
Keywords
SRAM, Decoder, Precharge Circuit, Sense Amplifier, Dummy column
Abstract
SRAM are useful building blocks in many applications such as cache memories, data storage embedded applications, microprocessors. The paper aims to propose the design for 128x128 SRAM with self time dummy replica technique for fast read & write access and low power consumption. The main functional blocks are 6T SRAM cell, row and column decoders, precharge circuit, read/write block and sense amplifier. Access time, speed & power consumption are the three key parameters for an SRAM memory design. Self time technique have been implemented to optimize power and access speed of SRAM. Memory timing circuits need a delay element which tracks the bit-line delay but still provide a large swing signal which can be used by the subsequent stages of the control logic. The key to building such a delay stage is to use a delay element which is a replica of the memory cell connected to the bit-line, while still providing a full swing output. This technique uses a dummy column and dummy row in the RAM to control the flow of signals through the core. The 128x128 SRAM has been designed, implemented & analyzed in standard TSMC 180nm technology library using Cadence Virtuoso tool.
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How To Cite (APA)
Mitali Agarwal & Taru Tevtia (April-2017). Design & Implementation of Self Time Dummy Replica Technique in 128x128 Low Voltage SRAM . INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT, 2(4), 110-115. https://ijnrd.org/papers/IJNRD1704029.pdf
Issue
Volume 2 Issue 4, April-2017
Pages : 110-115
Other Publication Details
Paper Reg. ID: IJNRD_160086
Published Paper Id: IJNRD1704029
Downloads: 000122253
Research Area: Engineering
Author Type: Indian Author
Country: Aligarh, Uttar Pradesh, India
Published Paper PDF: https://ijnrd.org/papers/IJNRD1704029.pdf
Published Paper URL: https://ijnrd.org/viewpaperforall?paper=IJNRD1704029
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