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INTERNATIONAL JOURNAL OF NOVEL RESEARCH AND DEVELOPMENT International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2456-4184 | Impact factor: 8.76 | ESTD Year: 2016 Scholarly open access journals, Peer-reviewed, and Refereed Journals, Impact factor 8.76 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool) , Multidisciplinary, Monthly, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI) |
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| Paper Title: | Design Of Low Power Synchronous Counter Using Adiabatic Techniques |
| Authors Name: | V. Hari Krishna , V. Bindu Priya , G.Raghu Ram , Ch.Dhanush , I.Sesha Talpa Sai |
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IJNRD_219357
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| Published Paper Id: | IJNRD2404745 |
| Published In: | Volume 9 Issue 4, April-2024 |
| DOI: | |
| Abstract: | In the designing of VLSI circuit’s power dissipation has become a major concern. So, by reducing power dissipation we can attain our low power circuit. Excessive power consumption can negatively impact circuit reliability, resulting in higher maintenance costs, which elevates the cost of cooling system and packaging. As, with the advancement of electronic circuits which are dealing with the digital circuitry are implemented with the use of CMOS technology. The simultaneous pursuit of high performance and low power consumption remains a paramount concern in contemporary integrated circuit design. Various adiabatic techniques can be used for minimizing the power Consumption. In the quest for ever-more efficient digital integrated circuits (ICs), adiabatic logic techniques have emerged as a promising alternative to traditional CMOS logic design. Adiabatic techniques aim to reduce power dissipation during signal transitions, potentially leading to significant improvements in circuit performance and energy efficiency. To evaluate their effectiveness, these techniques have been compared against established CMOS logic design principles in the context of specific circuit implementations, such as synchronous counters. The sequential circuit (Synchronous counter) is implemented with the use of adiabatic techniques like ecrl, 2n-2n2p etc |
| Keywords: | Complementary Metal Oxide Semiconductor(CMOS), N-channel metal-oxide semiconductor (NMOS), P-channel metal-oxide semiconductor (PMOS),Efficient Charge Recovery Logic(ECRL),Direct Current Diode Based Positive Feed Back Logic(DC DB PFAL) |
| Cite Article: | "Design Of Low Power Synchronous Counter Using Adiabatic Techniques", International Journal of Novel Research and Development (www.ijnrd.org), ISSN:2456-4184, Vol.9, Issue 4, page no.h379-h388, April-2024, Available :http://www.ijnrd.org/papers/IJNRD2404745.pdf |
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| ISSN: |
2456-4184 | IMPACT FACTOR: 8.76 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.76 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
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Published Paper ID:IJNRD2404745 Registration ID: 219357 Published In: Volume 9 Issue 4, April-2024 DOI (Digital Object Identifier): Page No: h379-h388 Country: Palnadu , District, Andhra Pradesh, India Research Area: Engineering Publisher : IJ Publication Published Paper URL : https://www.ijnrd.org/viewpaperforall?paper=IJNRD2404745 Published Paper PDF: https://www.ijnrd.org/papers/IJNRD2404745 |
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ISSN: 2456-4184
Impact Factor: 8.76 and ISSN APPROVED
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