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Paper Title: Design and Implementation of Parallel Self-Timed Adder Using VHDL
Authors Name: Dr. Ahmed Sajjad Khan , Mohammad Hassan , Syed Aiman , Shreya Raut , Shefali Gedam
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Published Paper Id: IJNRD1804007
Published In: Volume 3 Issue 4, April-2018
Abstract: As technology scales down into the lower nanometer values power, delay, area and frequency becomes important parameters for the analysis and design of any circuits. This brief presents a parallel single-rail self-timed adder. It is based on a recursive formulation for performing multi-bit binary addition. The operation is parallel for those bits that do not need any carry chain propagation. Thus, the design attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fan-outs. A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel. Simulations have been performed using industry standard toolkit that verify the practicality and superiority of the proposed approach over existing asynchronous adders.
Keywords: CMOS design, digital arithmetic Binary adders, Recursive adder.
Cite Article: "Design and Implementation of Parallel Self-Timed Adder Using VHDL ", International Journal of Novel Research and Development (, ISSN:2456-4184, Vol.3, Issue 4, page no.45-49, April-2018, Available :
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