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Paper Title: DCT Color Image Compression using VHDL
Authors Name: Mohammad Asif , Zakir Khan , Shahid Sayyede , Vasiullah , Prof. Syed Mohammad Ali
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Published Paper Id: IJNRD1803013
Published In: Volume 3 Issue 3, March-2018
Abstract: Digital images require large amounts of memory to be stored in a computer system. The JPEG compression standard allows the amount of memory storage required by a digital image to be reduced with little to no perceptible loss of image quality. This thesis is a design of an ASIC that implements a decoder of JPEG compressed images. The decoder implements the baseline decoder defined by the JPEG standard with a few exceptions, the most notable being that only grayscale images can be decompressed. With such an ASIC, the speed of decompressing images is greatly increased. The decoder was designed by writing VHDL source code, which in turn was used to synthesize the ASIC using standard cells. This paper describes a VHSIC Hardware Description Language (VHDL) simulation of a hardware 8x8 Discrete Cosine Transform (DCT) which can be applied to image compression. A Top-Down Design approach is taken in the study, a discussion of DCT theory is presented, along with a description of the 1-D DCT circuit architecture and its simulation in VHDL. Results of the 2-D DCT simulation are included for two simple test patterns and verified by hand calculation, demonstrating the validity of the simulation. Shortcoming found in the simulation are described, together with suggestions for correcting them. In the future, the VHDL description of the 8 x 8 image block 2-D DCT can be further developed into structural and gate-level description, after which hardware circuit implement can occur..
Keywords: DCT,Modelsim,SNR,ASCII,Zigzag.
Cite Article: "DCT Color Image Compression using VHDL ", International Journal of Novel Research and Development (, ISSN:2456-4184, Vol.3, Issue 3, page no.56-60, March-2018, Available :
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